Instead of separately transmitting a clock and a data stream, high speed electronic digital data communication systems often transmit only the data stream to achieve a better bandwidth. A clock and data recover (CDR) circuit within a receiver may recover a clock signal from the incoming data stream. The clock may be recovered using edges within the incoming data stream. Once the clock is recovered, it may be used to sample the data stream to recover the individual bits in the data stream. To meet stringent bit error rate (BER) requirement (e.g., less that 10−15), the incoming data stream at the receiver should be optimally sampled, requiring reliable and accurate clock recovery by the CDR circuit.